View LT3150CGNTR_6533999.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 lt3150 3150f fast transient response, low input voltage, very low dropout linear regulator controller 1.8v to 1.5v, 4a very low dropout linear regulator (typical dropout voltage = 65mv at i out = 4a) 50mv/div 2a/div 20 m s/div 3150 ta02 transient response for 0.1a to 4a output load step n microprocessor, asic and i/o supplies n very low dropout input-to-output conversion n logic termination supplies n fast transient response optimized with ceramic output capacitors n fet r ds(on) defines dropout voltage n 1% reference tolerance over temperature n multifunction ldo shutdown pin with latchoff n fixed frequency 1.4mhz boost converter generates mosfet gate drive n internally compensated boost converter uses tiny capacitors and inductor n independent boost converter shutdown control permits ldo output voltage supply sequencing n 16-lead ssop package the lt ? 3150 drives a low cost external n-channel mosfet as a source follower to produce a fast transient response, very low dropout voltage linear regulator. selection of the n-channel mosfet r ds(on) allows dropout voltages below 300mv for low v in to low v out applications. the lt3150 includes a fixed frequency boost regulator that generates gate drive for the n-channel mosfet. the internally compensated current mode pwm architecture combined with the 1.4mhz switching frequency permits the use of tiny, low cost capacitors and inductors. the lt3150s transient load performance is optimized with ceramic output capacitors. a precision 1.21v refer- ence accommodates low voltage supplies. protection includes a high side current limit amplifier that activates a fault timer circuit. a multifunction shutdown pin provides either current limit time-out with latchoff, overvoltage protection or thermal shutdown. independent shutdown control of the boost converter provides on/off and sequencing control of the ldo output voltage. + v in2 fb1 shdn2 swgnd gnd gnd sw v in1 shdn1 i pos i neg gate fb2 comp lt3150 mbr0520l l1 10 h 1.5k c in : panasonic sp series eefue0e221r 20% c1: avx taja475m020r 20v 20% l1: murata lqh32cn100k11 or sumida cdrh3d16100 243 1% 1020 1% c1 4.7 f + c in 220 f 2.5v 2 v in 1.8v v out 1.5v 4a 6.19k 1% 1.37k 1% si4410 3150 ta01 2.2 f 10 x5r ceramic 0805 case 5.1 6800pf 50pf descriptio u features applicatio s u typical applicatio u , ltc and lt are registered trademarks of linear technology corporation.
2 lt3150 3150f (note 1) v in1 , shdn1 voltage .............................................. 10v sw voltage .............................................. C 0.4v to 36v fb1 voltage ................................................ v in1 + 0.3v current into fb1, fb2 pin .................................... 1ma v in2 , i pos , i neg ....................................................... 22v shdn2 .................................................................... v in2 operating ambient temperature range ..... 0 c to 70 c junction temperature (note 2) ........................... 125 c storage temperature range ................ C 65 c to 150 c lead temperature (soldering, 10 sec)................. 300 c absolute axi u rati gs w ww u package/order i for atio uu w gn package 16-lead plastic ssop 1 2 3 4 5 6 7 8 top view 16 15 14 13 12 11 10 9 sw swgnd v in1 shdn2 v in2 gnd nc fb2 fb1 gnd shdn1 i pos i neg gate nc comp order part number lt3150cgn gn part marking 3150 t jmax = 125 c, q ja = 130 c/w, q jc = 40 c/w consult ltc marketing for parts specified with wider operating temperature ranges. electrical characteristics the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v in1 = 1.5v, v shdn1 = v in1 , v in2 = 12v, gate = 6v, i pos = i neg = 5v, v shdn2 = 0.75v unless otherwise noted. symbol parameter conditions min typ max units boost switching regulator v in1 minimum operating voltage 0.9 1.1 v v in1 maximum operating voltage 10 v v fb1 fb1 reference voltage l 1.20 1.23 1.255 v fb1 input bias current current flows into pin l 27 80 na i q1 v in1 quiescent current v shdn1 = 1.5v 3 4.5 ma v in1 quiescent current in shutdown v shdn1 = 0v, v in1 = 2v 0.01 0.5 m a v shdn1 = 0v, v in1 = 5v 0.01 1.0 m a fb1 reference line regulation 1.5v v in1 10v 0.02 0.2 %/v switching frequency l 1 1.4 1.9 mhz maximum duty cycle l 82 86 % switch current limit (note 3) 550 800 ma switch v cesat i sw = 300ma 300 350 mv switch leakage current v sw = 5v 0.01 1 m a shdn1 input voltage high 1 v shdn1 input voltage low 0.3 v shdn1 input bias current v shdn1 = 3v, current flows into pin 25 50 m a v shdn1 = 0v, current flows into pin 0.01 0.1 m a linear regulator controller i q2 v in2 quiescent current l 51219 ma v fb2 fb2 reference voltage 1.203 1.210 1.217 v l 1.198 1.210 1.222 v fb2 line regulation 10v v in2 20v l 0.01 0.03 %/v fb2 input bias current fb2 = v fb2 , current flows out of pin l C0.6 C4 m a
3 lt3150 3150f symbol parameter conditions min typ max units a vol large-signal voltage gain v gate = 3v to 10v l 69 84 db v ol gate output swing low (note 4) i gate = 0ma l 2.5 3 v v oh gate output swing high i gate = 0ma l v in2 C 1.6 v in2 C 1 v i pos + i neg supply current 3v i pos 20v l 0.3 0.625 1 ma current limit threshold voltage 42 50 58 mv l 37 50 63 mv current limit threshold voltage 3v i pos 20v l C 0.20 C 0.50 %/v line regulation shdn2 sink current current flows into pin l 2.5 5.0 8.0 m a shdn2 source current current flows out of pin l C8 C15 C23 m a shdn2 low clamp voltage l 0.1 0.25 v shdn2 high clamp voltage l 1.50 1.85 2.20 v shdn2 threshold voltage l 1.18 1.21 1.240 v shdn2 threshold hysteresis l 50 100 150 mv note 1: absolute maximum ratings are those values beyond which the life of the device may be impaired. note 2: t j is calculated from the ambient temperature t a and power dissipation p d according to the following formula: t j = t a + (p d ? 130 c/w) electrical characteristics the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v in1 = 1.5v, v shdn1 = v in1 , v in2 = 12v, gate = 6v, i pos = i neg = 5v, v shdn2 = 0.75v unless otherwise noted. note 3: switch current limit is guaranteed by design and/or correlation to static test. note 4: the v gs(th) of the external mosfet must be greater than 3v C v out .
4 lt3150 3150f switch v cesat vs switch current shdn1 input bias current vs v shdn1 oscillator frequency vs temperature fb2 reference voltage vs temperature switch current limit vs duty cycle fb1 reference voltage vs temperature fb2 input bias current vs temperature typical perfor a ce characteristics uw switch current (ma) 0 100 200 300 400 500 600 700 v cesat (mv) 3150 g01 700 600 500 400 300 200 100 0 t a = 25 c temperature ( c) 50 25 0 25 50 75 100 switching frequency (mhz) 3150 g02 2.00 1.75 1.50 1.25 1.00 0.75 0.50 0.25 0 v in = 5v v in = 1.5v shdn1 pin voltage (v) 012345 shdn1 input bias current ( a) 3150 g03 50 40 30 20 10 0 t a = 25 c duty cycle (%) 10 20 30 40 50 60 70 80 switch current limit (ma) 3150 g04 1000 900 800 700 600 500 400 300 200 70 c 25 c ?0 c temperature ( c) ?0 fb1 reference voltage (v) 3150 g05 1.25 1.24 1.23 1.22 1.21 1.20 voltage 25 0 25 50 75 100 temperature ( c) ?5 fb2 reference voltage (v) 1.210 1.214 1.218 1.222 125 3150 g07 1.206 1.202 1.208 1.212 1.216 1.220 1.204 1.200 1.198 ?5 25 75 50 150 0 50 100 175 temperature ( c) ?5 fb2 input bias current ( m a) 3.0 4.0 125 3150 g08 2.0 1.0 2.5 3.5 1.5 0.5 0 ?5 25 75 50 150 0 50 100 175 v in = 20v v in = 12v v in = 8v boost switching regulator v in2 quiescent current vs temperature temperature ( c) ?5 5 v in2 quiescent current (ma) 7 9 11 19 15 ?5 25 50 150 17 13 6 8 10 18 14 16 12 ?0 0 75 100 125 175 3150 g06 v in = 8v v in = 12v v in = 20v linear regulator controller
5 lt3150 3150f gain and phase vs frequency error amplifier large-signal voltage gain vs temperature gate output swing high (v in2 C v gate ) vs temperature i pos + i neg supply current vs temperature gate output swing low vs temperature current limit threshold voltage vs temperature current limit threshold voltage line regulation vs temperature temperature ( c) ?5 large-signal voltage gain (db) 105 115 125 3150 g10 95 85 100 110 120 90 80 75 70 ?5 25 75 50 150 0 50 100 175 frequency (hz) 50 100 error amplifier gain (db) and phase (deg) 150 200 1k 100k 1m 100m 3150 g11 0 10k 10m phase gain temperature ( c) ?5 gate output swing low (v) 2.50 3.00 125 3150 g12 2.00 1.50 2.25 2.75 1.75 1.25 1.00 ?5 25 75 50 150 0 50 100 175 i load = 50ma no load temperature ( c) 0 gate output swing high (v) 1.0 2.0 3.0 0.5 1.5 2.5 25 25 75 125 3150 g13 175 ?0 75 0 50 100 150 no load i load = 50ma temperature ( c) ?5 300 i pos + i neg supply current ( m a) 400 600 700 800 1000 ?0 50 100 3150 g14 500 900 25 150 175 ?5 0 75 125 i pos = i neg = 3v i pos = i neg = 5v i pos = i neg = 12v i pos = i neg = 20v temperature ( c) 35 current limit threshold voltage (mv) 45 55 65 40 50 60 25 25 75 125 3150 g15 175 ?0 75 0 50 100 150 i pos = 5v i pos = 3v i pos = 20v temperature ( c) ?5 current limit threshold voltage line regulation (%/v) 0.2 0.1 0 125 3150 g16 0.3 0.4 0.5 ?5 25 75 50 150 0 50 100 175 shdn2 sink current vs temperature temperature ( c) ?5 shdn2 sink current ( m a) 5.5 6.5 7.5 125 3150 g17 4.5 3.5 5.0 6.0 7.0 4.0 3.0 2.5 ?5 25 75 50 150 0 50 100 175 typical perfor a ce characteristics uw fb2 line regulation vs temperature temperature ( c) 0 fb2 line regulation (%/v) 0.010 0.020 0.030 0.005 0.015 0.025 25 25 75 125 3150 g09 175 ?0 75 0 50 100 150 linear regulator controller
6 lt3150 3150f shdn2 low clamp voltage vs temperature shdn2 hysteresis vs temperature shdn2 high clamp voltage vs temperature typical perfor a ce characteristics uw temperature ( c) ?5 shdn2 low clamp voltage (v) 0.15 0.20 0.25 125 3150 g19 0.10 0.05 0 ?5 25 75 50 150 0 50 100 175 temperature ( c) 1.5 shdn2 high clamp voltage (v) 1.7 1.9 2.1 1.6 1.8 2.0 25 25 75 125 3150 g20 175 ?0 75 0 50 100 150 temperature ( c) ?5 shdn2 hysteresis (mv) 110 130 150 125 3150 g21 90 70 100 120 140 80 60 50 ?5 25 75 50 150 0 50 100 175 uu u pi fu ctio s sw (pin 1): boost converter switch pin. connect induc- tor/diode here. minimize trace area at this pin to keep emi down. swgnd (pin 2): switch ground. tie directly to the local ground plane and the gnds at pins 6 and 15. v in1 (pin 3): boost converter input supply pin. must be locally bypassed. shdn2 (pin 4): this is a multifunction shutdown pin that provides gate drive latchoff capability. a 15 m a current source, that turns on when current limit is activated, charges a capacitor placed in series with shdn2 to gnd and performs a current limit time-out function. the pin is also the input to a comparator referenced to v ref (1.21v). when the pin pulls above v ref , the comparator latches the gate drive to the external mosfet off. the comparator typically has 100mv of hysteresis and the shdn2 pin can be pulled low to reset the latchoff function. this pin provides overvoltage protection or thermal shutdown protection when driven from various resistor divider schemes. temperature ( c) ?5 shdn2 source current ( m a) ?5 ?3 ?1 125 3150 g18 ?7 ?9 ?6 ?4 ?2 ?8 ?0 ?0 ?5 25 75 50 150 0 50 100 175 shdn2 source current vs temperature linear regulator controller
7 lt3150 3150f v in2 (pin 5): this is the input supply for the linear regulator control circuitry and provides sufficient gate drive compli- ance for the external n-channel mosfet. the maximum operating v in2 is 20v and the minimum operating v in2 is set by v out + (v gs of the mosfet at max i out ) + 1.6v (worst-case v in2 to gate output swing). gnd (pin 6): analog ground. this pin is also the negative sense terminal for the internal 1.21v reference. connect the ldo regulator external feedback divider network and fre- quency compensation components that terminate to gnd directly to this pin for best regulation and performance. also, tie this pin directly to swgnd (pin 2) and gnd (pin 15). nc (pins 7, 10): no connect. fb2 (pin 8): this is the inverting input of the error amplifier for the linear regulator. the noninverting input is tied to the internal 1.21v reference. input bias current for this pin is typically 0.6 m a flowing out of the pin. tie this pin to a resistor divider network to set output voltage. tie the top of the external resistor divider directly to the output load for best regulation performance. comp (pin 9): this is the high impedance gain node of the error amplifier and is used for external frequency compen- sation. the transconductance of the error amplifier is 15 millimhos and open-loop voltage gain is typically 84db. frequency compensation is generally performed with a series rc + c network to ground. gate (pin 11): this is the output of the error amplifier that drives n-channel mosfets with up to 5000pf of effective gate capacitance. the typical open-loop out- put impedance is 2 w . when using low input capacitance mosfets (< 1500pf), a small gate resistor of 2 w to 10 w dampens high frequency ringing created by an lc reso- nance due to the mosfet gates lead inductance and input capacitance. the gate pin delivers up to 50ma for a few hundred nanoseconds when slewing the gate of the n-channel mosfet in response to output load current transients. i neg (pin 12): this is the negative sense terminal of the current limit amplifier. a small sense resistor is connected in series with the drain of the external mosfet and is connected between the i pos and i neg pins. a 50mv threshold voltage in conjunction with the sense resistor value sets the current limit level. the current sense resis- tor can be a low value shunt or can be made from a piece of pc board trace. if the current limit amplifier is not used, tie the i neg pin to i pos to defeat current limit. an alternative is to ground the i neg pin. this action disables the current limit amplifier and additional internal circuitry activates the timer circuit on the shdn2 pin if the gate pin swings to the v in rail. this option provides the user with a no r sense tm current limit function. i pos (pin 13): this is the positive sense terminal of the current limit amplifier. tie this pin directly to the main input voltage from which the output voltage is regulated. shdn1 (pin 14): boost regulator shutdown pin. tie to 1v or more to enable device. ground to shut down. this pin must not float for proper operation. connect shdn1 externally as it does not incorporate an internal pull-up or pull-down. gnd (pin 15): boost converter analog ground. this pin is also the negative sense terminal for the fb1 1.23v reference. connect the external feedback divider net- work, which sets the v in2 supply voltage and terminates to gnd, directly to this pin for best regulation and performance. also, tie this pin directly to swgnd (pin 2) and gnd (pin 6). fb1 (pin 16): boost regulator feedback pin. reference voltage is 1.23v. connect resistive divider tap here. minimize trace area at fb1. set v out = v in2 according to v out = 1.23v(1 + r1/r2). uu u pi fu ctio s no r sense is a trademark of linear technology corporation.
8 lt3150 3150f block diagra s w sw2 normally closed i 2 5 m a + error amp comp 3150 bd02 + comp1 q9 shdn2 v in2 gnd fb2 r10 5k sw1 normally open 100mv hysteresis i 1 15 m a i 3 100 m a + i lim2 amp v th1 50mv + v th2 1v + d1 i pos i neg gate d2 + comp2 + comp3 or2 start-up v ref 1.21v r9 50k or1 q7 q6 q5 q4 q8 4 5 6 8 r8 (external) r7 (external) v out fb2 9 11 12 13 + + ff rq s 0.15 w sw driver comparator 2 shutdown shdn1 14 1 + s ramp generator r c 100k c c 40pf 1.4mhz oscillator swgnd 3150 bd1 r6 40k r4 140k r3 30k q2 x10 q1 q3 r2 (external) r1 (external) r5 40k v in2 v in1 v in1 3 fb1 fb1 16 gnd 15 a2 a1 i lim1 g m = 77 mhos boost switching regulator linear regulator controller
9 lt3150 3150f applicatio s i for atio wu uu introduction with each new generation of computing systems, total power increases while system voltages fall. cpu core, logic and termination supplies below 1.8v are now com- mon. power supplies must not only regulate low output voltages, but must also operate from low input voltages. a low voltage, very low dropout linear regulator is an attractive conversion option for applications with output current in the range of several amperes. component count and cost are low in comparison with switching regulator solutions and with low input-to-output differential volt- ages, efficiencies are comparable. in addition to low input-to-output voltage conversion, these systems require stringent output voltage regulation. the output voltage specification includes input voltage change, output load current change, temperature change and output load current transient response. total toler- ances as low as 2% are now required. for a 1.5v output voltage, this amounts to a mere 30mv. transient load current response is the most critical component as output current can cycle from zero to amps in tens of nanosec- onds. these requirements mandate the need for a very accurate, very high speed regulator. historically employed solutions include monolithic 3-terminal linear regulators, pnp transistors driven by low cost control circuits and simple buck converter switching regulators. the 3-terminal regulator provides high integration, the pnp driven regulator provides low dropout performance and the switching regulator pro- vides high electrical efficiency. however, these solutions manifest a common trait of transient response measured in many microseconds. this fact translates to a regulator output decoupling capacitor scheme requiring several hundred microfarads of very low esr bulk capacitance using multiple capacitors in parallel. this required bulk capacitance is in addition to the ceramic decoupling capacitor network that handles the transient load response during the first few hundred nanoseconds as well as providing high frequency noise immunity. the combined cost of all capacitors is a significant percentage of the total power supply cost. the lt3150 controller ic is a unique, easy-to-use device that drives an external n-channel mosfet as a source follower and realizes an extremely low dropout, ultrafast transient response regulator. the circuit achieves supe- rior regulator bandwidth and transient load performance by eliminating expensive special polymer, tantalum or bulk electrolytic capacitors in the most demanding appli- cations. performance is optimized around the latest gen- eration of low cost, low esr, readily available ceramic capacitors. users benefit directly by saving significant cost as all bulk capacitance is removed. additional savings include insertion cost, purchasing/inventory cost and board space. the precision-trimmed adjustable voltage lt3150 ac- commodates most power supply voltages. proper selec- tion of the n-channel mosfet r ds(on) allows user-settable dropout voltage performance. transient load step perfor- mance is optimized for ceramic output capacitor networks allowing the regulator to respond to transient load changes in a few hundred nanoseconds. the output capacitor network typically consists of multiple 1 m f to 10 m f ceramic capacitors in parallel depending on the power supply requirements. the lt3150 also incorporates current lim- iting, on/off control for power supply sequencing and overvoltage protection or thermal shutdown with simple external components. the lt3150 combines the benefits of low input voltage operation, very low dropout voltage performance, preci- sion regulation and fast transient response. with low input/output differential voltage applications becoming the norm, an lt3150-based solution is a practical alterna- tive to switching regulators providing comparable effi- ciency performance at an appreciable cost savings. block diagram operation gate drive for the external n-channel mosfet in the linear regulator loop is provided by a current mode, internally compensated, fixed frequency step-up switching regula- tor. referring to the block diagram, q1 and q2 form a bandgap reference core whose loop is closed around the output of the regulator. the voltage drop across r5 and r6
10 lt3150 3150f applicatio s i for atio wu uu is low enough such that q1 and q2 do not saturate, even when v in1 is 1v. when there is no load, fb1 rises slightly above 1.23v, causing v c (the error amplifiers output) to decrease. comparator a2s output stays high, keeping switch q3 in the off state. as increased output loading causes the fb1 voltage to decrease, a1s output increases. switch current is regulated directly on a cycle-by-cycle basis by the v c node. the flip flop is set at the beginning of each switch cycle, turning on the switch. when the summation of a signal representing switch current and a ramp generator (introduced to avoid subharmonic oscilla- tions at duty factors greater than 50%) exceeds the v c signal, comparator a2 changes state, resetting the flip flop and turning off the switch. more power is delivered to the output as switch current is increased. the output voltage, attenuated by external resistor divider r1 and r2, appears at the fb1 pin, closing the overall loop. frequency com- pensation is provided internally by r c and c c . transient response can be optimized by the addition of a phase lead capacitor c pl in parallel with r1 in applications where large value or low esr output capacitors are used. as the load current is decreased, the switch turns on for a shorter period each cycle. if the load current is further decreased, the converter will skip cycles to maintain output voltage regulation. the linear regulator controller section of the lt3150 block diagram consists of a simple feedback control loop and multiple protection functions. examining the block dia- gram for the lt3150, a start-up circuit provides controlled start-up, including the precision-trimmed bandgap refer- ence, and establishes all internal current and voltage biasing. reference voltage accuracy at the fb2 pin is specified as 0.6% at room temperature and as 1% over the full operating temperature range. this places the lt3150 among a select group of regulators with a very tightly specified reference voltage tolerance. the 1.21v reference is tied to the noninverting input of the main error amplifier in the feedback control loop. the error amplifier consists of a single high gain g m stage with a transconductance equal to 15 millimhos. the inverting terminal is brought out as the fb2 pin. the g m stage provides differential-to-single ended conversion at the comp pin. the output impedance of the g m stage is about 1m w and thus, 84db of typical dc error amplifier open-loop gain is realized along with a typical 75mhz uncompensated unity-gain crossover frequency. note that the overall feedback loops dc gain decreases from the gain provided by the error amplifier by the attenuation factor in the resistor divider network which sets the dc output voltage. external access to the high impedance gain node of the error amplifier permits typical loop compensation to be accomplished with a series rc + c network to ground. a high speed, high current output stage buffers the comp node and drives up to 5000pf of effective mosfet gate capacitance with almost no change in load transient per- formance. the output stage delivers up to 50ma peak when slewing the mosfet gate in response to load current transients. the typical output impedance of the gate pin is typically 2 w . this pushes the pole due to the error amplifier output impedance and the mosfet input capacitance well beyond the loop crossover frequency. if the capacitance of the mosfet used is less than 1500pf, it may be necessary to add a small value series gate resistor of 2 w to 10 w . this gate resistor helps damp the lc resonance created by the mosfet gates lead induc- tance and input capacitance. in addition, the pole formed by this resistance and the mosfet input capacitance can be fine tuned. because the mosfet pass transistor is connected as a source follower, the power path gain is much more predict- able than designs that employ a discrete pnp transistor as the pass device. this is due to the significant production variations encountered with pnp beta. mosfets are also very high speed devices which enhance the ability to pro- duce a stable wide bandwidth control loop. an additional advantage of the follower topology is inherently good line rejection. input supply disturbances do not propagate through to the output. the feedback loop for a regulator circuit is completed by providing an error signal to the fb2 pin. a resistor divider network senses the output voltage and sets the regulated dc bias point. in general, the lt3150 regulator feedback loop permits a loop crossover frequency on the order of 1mhz while maintaining good phase and gain margins. this unity-gain frequency is a factor of 20 to 30 times the bandwidth of currently implemented regulator
11 lt3150 3150f applicatio s i for atio wu uu solutions for microprocessor power supplies. this signifi- cant performance benefit is what permits the elimination of all bulk output capacitance. several other unique features are included in the design that increase its functionality and robustness. these func- tions comprise the remainder of the block diagram. a high side sense, current limit amplifier provides active current limiting for the regulator. the current limit ampli- fier uses an external low value shunt resistor connected in series with the external mosfets drain. this resistor can be a discrete shunt resistor or can be manufactured from a kelvin-sensed section of free pc board trace. all load current flows through the mosfet drain and thus, through the sense resistor. the advantage of using high side current sensing in this topology is that the mosfets gain and the main feedback loops gain remain unaffected. the sense resistor develops a voltage equal to i out (r sense ). the current limit amplifiers 50mv threshold voltage is a good compromise between power dissipation in the sense resistor, dropout voltage impact and noise immunity. current limit activates when the sense resistor voltage equals the 50mv threshold. two events occur when current limit activates: the first is that the current limit amplifier drives q5 in the block diagram and clamps the positive swing of the comp node in the main error amplifier to a voltage that provides an output load current of 50mv/r sense . this action contin- ues as long as the output current overload persists. the second event is that a timer circuit activates at the shdn2 pin. this pin is normally held low by a 5 m a active pull-down that limits to ? 100mv above ground. when current limit activates, the 5 m a pull-down turns off and a 15 m a pull-up current source turns on. placing a capacitor in series with the shdn2 pin to ground generates a programmable time ramp voltage. the shdn2 pin is also the positive input of comp1. the negative input is tied to the internal 1.21v reference. when the shdn2 pin ramps above v ref , the comparator drives q7 and q8. this action pulls the comp and gate pins low and latches the external mosfet drive off. this condition reduces the mosfet power dissipation to zero. the time period until the latched-off condition occurs is typically equal to c shdn2 (1.11v)/15 m a. for example, a 1 m f capacitor on the shdn2 pin yields a 74ms ramp time. in short, this unique circuit block performs a current limit time-out function that latches off the regulator drive after a predefined time period. the time-out period selected is a function of system requirements including start-up and safe operating area. the shdn2 pin is internally clamped to typically 1.85v by q9 and r10. the comparator tied to the shdn2 pin has 100mv of typical hysteresis to provide noise immunity. the hysteresis is especially useful when using the shdn2 pin for thermal shutdown. restoring normal operation after the load current fault is cleared is accomplished in two ways. one option is to recycle the v in2 lt3150 supply voltage as long as an external bleed path for the shdn2 pin capacitor is pro- vided. the second option is to provide an active reset circuit that pulls the shdn2 pin below v ref . pulling the shdn2 pin below v ref turns off the 15 m a pull-up current source and reactivates the 5 m a pull-down. if the shdn2 pin is held below v ref during a fault condition, the regu- lator continues to operate in current limit into a short. this action requires being able to sink 15 m a from the shdn2 pin at less than 1v. the 5 m a pull-down current source and the 15 m a pull-up current source are designed low enough in value so that an external resistor divider network can drive the shdn2 pin to provide overvoltage protection or to provide thermal shutdown with the use of a thermistor in the divider network. diode-oring these functions to- gether is simple to accomplish and provides multiple functionality for one pin. if the current limit amplifier is not used, two choices present themselves. the simplest choice is to tie the i neg pin directly to the i pos pin. this action defeats current limit and provides the simplest, no frills circuit. applications in which the current limit amplifier is not used are where extremely low dropout voltages must be achieved and the 50mv threshold voltage cannot be tolerated. however, a second available choice permits a user to pro- vide short-circuit protection with no external sensing. this technique is activated by grounding the i neg pin. this action disables the current limit amplifier because schottky diode d1 clamps the amplifiers output and prevents q5 from pulling down the comp node. in addition, schottky diode d2 turns off pull-down transistor q4. q4 is normally on and
12 lt3150 3150f applicatio s i for atio wu uu holds internal comparator comp3s output low. this comparator circuit, now enabled, monitors the gate pin and detects saturation at the positive rail. when a saturated condition is detected, comp3 activates the shutdown timer. once the time-out period occurs, the output is shut down and latched off. the operation of resetting the latch remains the same. note that this technique does not limit the fet current during the time-out period. the output current is only limited by the input power supply and the input/out- put impedance. setting the timer to a short period in this mode of operation keeps the external mosfet within its soa (safe operating area) boundary and keeps the mosfets temperature rise under control. unique circuit design incorporated into the lt3150 allevi- ates all concerns about power supply sequencing. the issue of power supply sequencing is an important topic as the typical lt3150 application has two separate power supply inputs, v in1 and v in2 . if the v in2 supply voltage is slow in ramping up or is held off by shdn1, insufficient mosfet gate drive exists and therefore, the output voltage does not come up. this statement is true as long as the v in1 input voltage is lower than the threshold of the external mosfet. prior to the boost converter powering up, v in2 equals v in1 C v f due to the dc path present through the boost inductor. if v in1 is high enough, the mosfet turns on and pulls the output voltage up. if this situation exists and the output must be held off, then pulling the shdn2 pin high actively holds the output off. pull the shdn2 pin low to allow start-up, as the shdn2 high logic state is a latched condition. if v in2 is present, but the v in1 supply voltage tied to the i pos pin is slow in ramping, then the feedback loop wants to drive the gate pin to the positive v in2 rail. this results in a large current as the v in1 supply ramps up. however, undervoltage lockout circuit comp2, which monitors the i pos supply voltage, holds q6 on and pulls the comp pin low until the i pos voltage increases to greater than the internal 1.21 reference voltage. the undervoltage lockout circuit then smoothly releases the comp pin and allows the output voltage to come up in dropout from the input supply voltage. an additional benefit derived from the speed of the lt3150 feedback loop is that turn-on overshoot is virtually nonexistent in a properly compen- sated system. boost regulator component selection diode linear technology recommends the use of a schottky diode with the lt3150. for input supply voltages less than 2v, the motorola mbr0520 or equivalent is a good choice due to its small size, low cost and low forward voltage. the average diode current equals the v in2 supply current of 12ma typically. the peak diode current equals the peak switch current, which in these low input-to-output voltage applications ranges from 100ma to 200ma. the diodes forward voltage during its conduction period directly affects the duty cycle of the boost converter. these low input-to-output voltage applications require the boost converter to operate at duty cycles close to the maximum and the difference of a few hundred millivolts in the diode forward voltage results in a duty cycle difference of several percent. for supply voltages greater than 2v, a 1n4148 is suitable and lowers cost. inductor use inductors with a saturation current rating (where inductance is approximately 70% of zero current induc- tance) of 0.2a or greater. also, choose an inductor with a dcr of 2.5 w or less. the inductors dcr also affects the boost converters duty cycle. a larger dcr value increases the required duty cycle. an inductance value between 4.7 m h and 10 m h works well in most applications. table 1 lists several 10 m h inductors that work with the lt3150, although this is by no means an exhaustive list. many magnetic vendors have components suitable for use in this boost application. input capacitor the input bypass capacitors serve as the reservoir capaci- tor for the boost regulator, the linear regulator and what- ever other system circuitry the input supply powers. therefore, the input capacitor network is most likely distributed along the input supply pcb plane. however, the switching of current at high speed by the boost regulator mandates a local bypass capacitor at the v in1 pin. place this input capacitor physically close to the
13 lt3150 3150f table 1. inductor vendors vendor phone url part number inductance dcr i sat murata (404) 436-1300 www.murata.com lqh31cn100k03k 10 m h 1.3 w 0.23a lqh32cn100k23k 10 m h 0.44 w 0.3a panasonic (800) 344-2112 www.panasonic.com eljpc100kf 10 m h 2.2 w 0.21a sumida (847) 956-0666 www.sumida.com cdrh3d16100 10 m h 0.21 w 0.55a taiyo yuden (800) 348-2496 www.t-yuden.com lqlb2016t100m 10 m h 0.5 w 0.155a lqlb2518t100m 10 m h 0.25 w 0.165a toko (847) 297-0070 www.toko.com llm3225-100k 10 m h 1.7 w 0.22a applicatio s i for atio wu uu v in1 pin. esr is not critical and in most cases, an inexpen- sive tantalum or ceramic capacitor with a value from 1 m f to 4.7 m f is appropriate. output capacitor the output capacitor choice is far more important. the capacitors characteristics determines output voltage ripple. the output capacitor must have enough capacitance to satisfy the load under transient conditions and it must shunt the switched component of current coming through the diode. output voltage ripple results because this switched current passes through the capacitors finite output impedance. the capacitor must have low imped- ance at the 1.4mhz switching frequency of the lt3150. at this frequency, the capacitors equivalent series resis- tance (esr) usually dominates the impedance. choosing a capacitor with lower esr results in lower output voltage ripple. however, consider loop stability when choosing the out- put capacitor because the lt3150 is internally compen- sated and no access is provided to this internal compensation. small, low cost tantalum capacitors have some esr. this esr enhances stability due to the addition of a zero in the regulator feedback loop. ceramic capaci- tors are very popular, having attractive characteristics such as near-zero esr, small size and low cost. replacing the tantalum output capacitor with a ceramic unit de- creases the phase margin, in some cases to unacceptable levels. the addition of a phase lead capacitor and an isolating resistor in the feedback divider network can be used to stabilize the feedback loop, but the added compo- nent count and cost makes the use of a tantalum output capacitor the simpler and preferred choice. the boost regulator output capacitor also serves as the v in2 input bypass capacitor. place this capacitor physi- cally close to the v in2 pin. this capacitor supplies the instantaneous current to slew the external mosfets gate capacitance quickly during an output load current transient. linear regulator component selection output capacitors the lt3150 linear regulator is stable with a wide range of output capacitors (assuming the feedback loop is prop- erly frequency compensated). however, using multiple, low value, very low esr ceramic capacitors (1 m f to 4.7 m f) in parallel optimizes the load transient response of an lt3150 feedback loop. as is discussed in the frequency compensation section, the output capacitor value is criti- cal because it sets the location of a pole in the feedback loop that determines the unity-gain crossover frequency. therefore, the characteristics of ceramic capacitors war- rant some discussion. manufacturers make ceramic capacitors with a variety of dielectrics, each with different behavior across tempera- ture and applied voltage. the most common dielectrics are z5u, y5v, x5r and x7r. the z5u and y5v dielectrics provide high c-v products in a small package at low cost, but exhibit very strong voltage and temperature coeffi- cients. the x5r and x7r dielectrics yield highly stable characteristics and are more suitable for use as the output capacitor at fractionally increased cost. the x5r and x7r dielectrics both exhibit excellent voltage coefficient char ac- teristics. the x7r type works over a larger temperature range and exhibits better temperature stability whereas x5r is less expensive and is available in higher values.
14 lt3150 3150f applicatio s i for atio wu uu figure 1. ceramic capacitor dc bias characteristics figure 2. ceramic capacitor temperature characteristics dc bias voltage (v) change in value (%) 3150 f01 20 0 ?0 ?0 ?0 ?0 100 0 4 8 10 26 12 14 x5r y5v 16 both capacitors are 16v, 1210 case size, 10 f temperature ( c) ?0 40 20 0 ?0 ?0 ?0 ?0 100 25 75 3150 f02 ?5 0 50 100 125 y5v change in value (%) x5r both capacitors are 16v, 1210 case size, 10 f figures 1 and 2 show voltage coefficient and temperature coefficient comparisons between y5v and x5r material. with the critical pole in the lt3150 feedback loop being set by the absolute value of the output capacitor, it is obvious why linear technology strongly recommends the use of ceramic capacitors with x5r or x7r dielectric material. mosfet selection mosfet selection criteria include threshold voltage v gs(th) , maximum continuous drain current i d , on-resis- tance r ds(on) , maximum drain-to-source voltage v ds and package thermal resistance r th(ja) . linear technology recommends the use of a logic-level threshold mosfet in lt3150 applications. the v gs range, as defined by the threshold voltage and the load current range, fits well within the boost regulators capability and the output swing range of the error amplifier. the mosfets continuous drain current rating must equal or exceed the maximum load current and the maximum drain-to-source voltage must exceed the maximum input voltage. the most critical specification is the mosfet r ds(on) . calculate the required r ds(on) from the following formula: mosfet r ds(on) vv i in min out min out max () () () 3 the additional factor of three in the equations denomina- tor accounts for production variation, the temperature coefficient of r ds(on) , voltage dips in v in during transient output load steps and other operating point characteris- tics. although the factor of three is slightly conservative, this imposes no cost penalty. as an example, consider the 1.8v to 1.5v at 4a application on the front page. assuming the 1.8v input and the 1.5v output each have a 5% tolerance, r ds(on) =w (. . )(. . ) . 095 18 095 15 34 23 8 vv a m a siliconix si4410 mosfet with an r ds(on) of 20m w is a close match. although the si4410s 30v maximum v ds and 8a maximum i d ratings exceed the applications requirements, the si4410s low cost makes it an excellent choice. as the final criteria, consider the thermal resistance r th(ja) of the mosfets package. the temperature rise in the mosfet must be kept under control and within the manufacturers maximum junction temperature specifica- tion. the power dissipated in the mosfet is calculated by: p mosfet = (v in C v out ) ? i out in the design example, p mosfet = (1.8v C 1.5v) ? 4a = 1.2w. the si4410s r th(ja) is 50 c/w for its s0-8 pack- age, which translates to a 60 c temperature rise above ambient. mosfet manufacturers have significantly low- ered the thermal resistance of modern devices with im- proved packages. these packages provide exposed backsides that directly transfer heat to the pcb board. these packages enable lt3150 applications with much higher output currents while keeping the mosfet tem- perature in control.
15 lt3150 3150f applicatio s i for atio wu uu figure 3. simplified block diagram for frequency compensation + + v ref fb2 r o 1m r1 r f1 r esr r f2 r g v in v out i load 3150 f03 q1 c1 c2 comp g m1 = 0.015 c o v ref v out r f2 r f1 + r f2 = frequency compensation frequency compensation is the most critical step in de- signing an lt3150 application circuit. frequency compen- sation stabilizes the feedback loop under all line, load and temperature conditions and determines the transient load step performance. to start the frequency compensation process, gather the following application information. determine the output voltage, the minimum and maximum output currents, the transconductance (g fs ) of the selected mosfet at the minimum and maximum output currents and the output capacitor type (ceramic, tantalum, electrolytic). frequency compensation is accomplished with a passive network tied from the lt3150s comp pin to ground. the lt3150 generally employs a type-2 frequency compensa- tion method. the type-2 method uses two poles and one zero. the output capacitor type determines how the zero in the feedback loop is set. ceramic capacitors typically have very low esr (equivalent series resistance) and therefore the comp pin network sets the zero location. tantalum and electrolytic capacitors typically have suffi- cient esr such that the zero formed by the esr and the capacitance value is used. using tantalum or electrolytic capacitors in lt3150 applications is somewhat more challenging because the user must choose capacitors with the proper esr plus capacitance value to place the zero at the correct spot in the frequency response. refer to the simplified lt3150 block diagram shown in figure 3 during the frequency compensation discussion that follows. figure 4 illustrates the typical bode plot and the pole/zero locations with the use of low esr ceramic output capacitors. figure 5 illustrates the typical bode plot and the pole/zero locations with the use of tantalum or electrolytic output capacitors. in both output capacitor cases, the location of the first pole, p1, is set by the error amplifier comp pins open- loop output impedance, r o , and compensation capacitor, c1. the low frequency gain is set by g m1 ? r o ? (v ref /v out ) in the case of low esr ceramic capacitors, r1 in series with c1 in the comp pin network sets the zero, z1. with tantalum or electrolytic capacitors, the esr in series with the output capacitor c o sets z1. z1s location establishes the mid-band gain or shelf gain. for a given value of output capacitance, the shelf gain determines the regulators transient response to an output load step, especially the output voltages peak overshoot and under- shoot. for a given output load current change, a corre- sponding delta in the mosfets v gs occurs. this d v gs divided by the shelf gain sets how much the fb2 must change and thus, results in output voltage perturbation. higher shelf gain results in lower transient response peak deviations. higher shelf gain also translates to a
16 lt3150 3150f applicatio s i for atio wu uu figure 4. typical bode plot for low esr ceramic output capacitors gain (db) frequency (hz) p2 is a function of load current i load(min) many high order poles and zeros past unity-gain f x i load(max) 3150 f04 av1 = g m1 ?r1 ?(v ref /v out ) avol = g m1 ?r o ?(v ref /v out ) p2 = g m (q1)/(2 ? ?c o ) z1 = 1/(2 ? ?r1 ?c1) p1 = 1/(2 ? ?r o ?c1) v ref v out f x = g m1 ?r1 g m (q1) 2 ? ?c o gain (db) frequency (hz) p2 is a function of load current i load(min) many high order poles and zeros past unity-gain f x i load(max) 3150 f05 av1 = avol ?(p1/p2) = (g m1 ?c o )/(g m (q1) ?c1) avol = g m1 ?r o ?(v ref /v out ) p2 = g m (q1)/(2 ? ?c o ) z1 = 1/(2 ? ?esr ?c o ) p1 = 1/(2 ? ?r o ?c1) f x = g m1 2 ? ?c1 figure 5. typical bode plot for tantalum or electrolytic output capacitors higher unity gain bandwidth crossover frequency, f x . f x must be set to a value that provides adequate phase and gain margin and this criteria limits the shelf gain value. if higher shelf gain is required for a given application, then increase output capacitance. in both output capacitor cases, the location of the second pole, p2, is set by the mosfets transconductance, g m (q1), and the value of the output capacitor, c o . the output load current sets the transconductance of the mosfet. p2 moves as a function of load current and consequently, so does the unity-gain crossover frequency, f x . figures 4 and 5 depict this behavior. at very low output currents, p2s location moves to a very low frequency. therefore, set z1 at a low enough frequency to provide adequate phase boost. a temptation is to set z1s value equal to p2s value at minimum output load current. the bode plot then exhibits a single pole response at minimum output current. how- ever, this either makes the shelf gain and f x too high for stability or it makes the small signal settling time very long. set z1 above the minimum value for p2 so that at small output load currents, the second pole p2 occurs and then z1 provides phase boost prior to crossing unity gain. at the highest load current levels, several poles and zeros exist just beyond the unity-gain crossover frequency. sometimes, the gain peaks back above unity and a high frequency, low level oscillation appears. a high frequency pole is necessary to roll off the response. in the case of ceramic output capacitors, capacitor c2 in figure 4 sets this pole in combination with r1. in the case of electrolytic or tantalum output capacitors, some small ceramic ca- pacitors in parallel with the main output capacitors usually provide the desired response. finally, look for very high frequency gate oscillations in the range of 2mhz to 10mhz. small mosfets with low gate capacitance are most susceptible to this issue. this oscil- lation is typically caused by the mosfets effective gate capacitance and the mosfets parasitic source induc- tance resonating. the mosfets source inductance is the sum of the devices bond wire plus package lead induc- tance and the pcb trace inductance between the mosfets source and the actual output capacitors. although the mosfets internal inductance is fixed, proper pcb layout techniques minimize the external inductance. minimize the distance between the mosfets source and the output decoupling capacitors and run wide planes if possible. connect the top of the feedback divider at the point closest to the actual load rather than the mosfet source. if high frequency oscillations persist, a small value resistor in the range of 1 w to 50 w in series with the gate of the mosfet typically eliminates this ringing. the inclusion of a gate resistor may permit the high frequency pole discussed in the preceding paragraph to be eliminated or fine tuned.
17 lt3150 3150f setting the linear regulator output voltage using no r sense current limit shutdown time-out with reset overvoltage protection shutdown time-out with reset basic thermal shutdown setting current limit current limit with foldback limiting example typical applicatio s u fb2 3150 ta03 r2 v out = 1.21v(1 + r2/r1) v out r1 c1 10 m f d1 mbr0520l c t i pos shdn2 v in1 3150 ta04 v out q1 i neg gate i pos v in1 r sense * *i lim = 50mv/r sense r sense = discrete shunt resistor or r sense = kelvin-sensed pc board trace activating current limit also activates the shdn2 pin timer 3150 ta05 v out q2 i neg gate i pos v in1 i out r4 d1 1n4148 d2 1n4148 r5 3150 ta06 v out q3 i neg gate r6 50mv r4 set r5 << r6 i out = r6 r5 + r6 () r5 r5 + r6 () (v in1 ?v out ?2v f ) r4 r1 100k c1* 3150 ta07 *c1 = 15 m a(t)/1.11v t = shutdown latchoff time shdn2 q1 vn2222l reset 0v to 5v shdn2 3150 ta08 rt1 10k ntc v in1 r4* rt1 = dale nths-1206n02 thermally mount rt1 in close proximity to the external n-channel mosfet *choose r4 based on v in1 and required thermal shutdown temperature r3 100k r2 100k c2* 3150 ta09 *c2 = 15 m a(t)/1.11v t = shutdown latch-off time shdn2 q2 2n3904 reset 0v to 5v shdn2 3150 ta10 v out r5 r6 v out(uth) = 1.21(r6/r5) + 5 m a(r6) v out(lth) = 1.11(r6/r5) ?15 m a(r6)
18 lt3150 3150f typical applicatio s u 1.5v to 1.2v, 4a very low dropout linear regulator + v in2 fb1 shdn2 swgnd gnd gnd sw v in1 shdn1 i pos i neg gate fb2 comp lt3150 mbr0520l l1 10 h 1.5k c1 4.7 f + c in 220 f 2.5v 2 v in 1.5v v out 1.2v 4a 5.9k 1% 1.37k 1% si4410 3150 ta11 2.2 f 10 x5r ceramic 0805 case 5.1 6800pf 50pf c in : panasonic sp series eefue0e221r 20% c1: avx taja475m020r 20v 20% l1: murata lqh32cn100k11 or sumida cdrh3d16100 + v in2 fb1 shdn2 swgnd gnd gnd sw v in1 shdn1 i pos i neg gate fb2 comp lt3150 mbr0520l l1 10 h 1.5k 499 1% 1020 1% c1 4.7 f + c in 220 f 4v 2 v in 2.5v v out 1.8v 1.7a 6.65k 1% 1.37k 1% si4410 3150 ta11a 2.2 f 6 x5r ceramic 0805 case 5.1 6800pf 50pf c in : panasonic sp series eefue0g221r 20% c1: avx taja475m020r 20v 20% l1: murata lqh32cn100k11 or sumida cdrh3d16100 2.5v to 1.8v, 1.7a low dropout linear regulator
19 lt3150 3150f u package descriptio gn package 16-lead plastic ssop (narrow .150 inch) (reference ltc dwg # 05-08-1641) gn16 (ssop) 0502 12 3 4 5 6 7 8 .229 ?.244 (5.817 ?6.198) .150 ?.157** (3.810 ?3.988) 16 15 14 13 .189 ?.196* (4.801 ?4.978) 12 11 10 9 .016 ?.050 (0.406 ?1.270) .015 .004 (0.38 0.10) 45 0 ?8 typ .007 ?.0098 (0.178 ?0.249) .053 ?.068 (1.351 ?1.727) .008 ?.012 (0.203 ?0.305) .004 ?.0098 (0.102 ?0.249) .0250 (0.635) bsc .009 (0.229) ref .254 min recommended solder pad layout .150 ?.165 .0250 typ .0165 .0015 .045 .005 *dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side **dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side inches (millimeters) note: 1. controlling dimension: inches 2. dimensions are in 3. drawing not to scale information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
20 lt3150 3150f ? linear technology corporation 2002 lt/tp 1003 1k ? printed in the usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear.com related parts part number description comments lt1573 ultrafast transient response low dropout v in : 2.8v to 10v, v out : 1.265v, dropout voltage: 0.35v, i q : 1.7ma, regulator pnp driver, up to 5a i sd : 200 m a, requires external pnp transistor, s8 package lt1575/lt1577 ultrafast transient response low dropout v in : 1.5v to 22v, v out : 1.21v, dropout voltage: 0.15v, i q : 12ma, regulator mosfet driver, up to 10a lt1577 is dual version, n8, s8 packages lt1761 100ma, low noise micropower, ldo v in : 1.8v to 20v, v out : 1.22v, dropout voltage: 0.30v, i q : 20 m a, i sd : <1 m a, low noise <20 m v rms p-p , stable with 1 m f ceramic capacitors, thinsot package lt1762 150ma, low noise micropower, ldo v in : 1.8v to 20v, v out : 1.22v, dropout voltage: 0.30v, i q : 25 m a, i sd : <1 m a, low noise <20 m v rms p-p , ms8 package lt1763 500ma, low noise micropower, ldo v in : 1.8v to 20v, v out : 1.22v, dropout voltage: 0.30v, i q : 30 m a, i sd : <1 m a, low noise <20 m v rms p-p , s8 package lt1764/lt1764a 3a, low noise, fast transient response, ldo v in : 2.7v to 20v, v out : 1.21v, dropout voltage: 0.34v, i q : 1ma, i sd : <1 m a,low noise <40 m v rms p-p , a version stable with ceramic capacitors, dd, to220-5 packages lt1962 300ma, low noise micropower, ldo v in : 1.8v to 20v, v out : 1.22v, dropout voltage: 0.27v, i q : 30 m a, i sd : <1 m a, low noise <20 m v rms p-p , ms8 package lt1963/lt1963a 1.5a, low noise, fast transient response, ldo v in : 2.1v to 20v, v out : 1.21v, dropout voltage: 0.34v, i q : 1ma, i sd : <1 m a, low noise <40 m v rms p-p , a version stable with ceramic capacitors, dd, t0220-5, sot-223, s8 packages ltc3411 1.25a(i out ), 4mhz, synchronous step-down 95% efficiency, v in : 2.5v to 5.5v, i out : 1.25a, v ref : 0.8v, dc/dc converter i sd : <1 m a, ms and dfn packages ltc3412 2.5a(i out ), 4mhz, synchronous step-down 95% efficiency, v in : 2.5v to 5.5v, i out : 2.5a, v ref : 0.8v, dc/dc converter i sd : <1 m a, tssop16e package u typical applicatio 1.8v to 1.5v, 4a very low dropout linear regulator with no r sense current limiting and shutdown + v in2 fb1 shdn2 swgnd gnd gnd sw v in1 shdn1 i pos i neg gate fb2 comp lt3150 mbr0520l l1 10 h 10k shdn1 1.5k 243 1% 1020 1% c1 4.7 f 0.01 f shdn2 + c in 220 f 2.5v 2 v in 1.8v v out 1.5v 4a 6.19k 1% 1.37k 1% si4410 3150 ta11a 2.2 f 10 x5r ceramic 0805 case 5.1 bat54 6800pf 50pf 10 f c in : panasonic sp series eefue0e221r 20% c1: avx taja475m020r 20v 20% l1: murata lqh32cn100k11 or sumida cdrh3d16100

▲Up To Search▲

Price & Availability of LT3150CGNTR

	To Download LT3150CGNTR Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .